1. Field of the Invention
The invention relates generally to digital processors, and more specifically, to the efficient movement and the storage of data in registers of the processors.
2. Description of the Related Art
There has been much development in computers and processors to speed up the processing of data and optimize use of data path cycles. Many microprocessor applications require the movement of data from a source register resource to a destination register resource. This has generally been accomplished by the implementation of a move instruction or by the use of an add instruction applied to the source instructor with a constant zero second operand. Both of these methods consume the data path during the instruction cycle to accomplish the move.
FIG. 1 illustrates a prior art data path resource which may be used for data movement between registers. The figure shows a register file containing some number of register data locations and which has two ports for reading operands A and B, and a port for writing the destination W. Addresses for all these ports are driven by the control unit based on the decoding of the current instruction execution. For data movement to occur between two registers in the register file, an instruction is issued to select the source register as operand A and either operand B is ignored or expected to be a constant zero value. The destination is selected for the write port and the data movement is accomplished by the source passing through the ALU unmodified and written to the destination via the register file write port.
Other prior art has manipulated data and registers in a variety of methods. U.S. Pat. No. 5,019,969 issued May 28, 1991 in the name of Izumisawa et al. discloses a computer system for directly transferring vector elements from register to register using a single instruction. The system uses a dedicated hardware unit and data path which provides the data movement in parallel with any subsequent operations which the main ALU may perform. This dedicated hardware will consume an execution cycle for each data moved which will result in the variable time delay latency from the time the move instruction is issued until the time it is completed. This means that subsequent instructions which access the data can not be executed until the move is complete.
U.S. Pat. No. 4,586,131 issued Apr. 29, 1986 in the name of Caudel et al. discloses a microcomputer having data movement circuits for within-memory shift of data words. The data movement is accomplished by actual physical movement of the data storage from one circuit to another, and the multiple data shift would take an execution cycle per data moved.
U.S. Pat. No. 5,396,610 issued Mar. 7, 1995 in the name of Yoshida et al. discloses a register address specifying circuit for simultaneously accessing two registers when executing the instruction for transferring a plurality of registered contents.
U.S. Pat. No. 5,446,865 issued Aug. 29, 1995 in the name of Corcoran et al. discloses a processor adapted for use as a coprocessor for sharing memory with more than one processor.